Multi-mode DRAM controller

ABSTRACT

The present invention provides a novel multi-mode DRAM controller adaptd to access DRAM chips of a main storage unit of different size and of different mode types. The novel DRAM controller comprises new address generation and control logic for delaying the RAS and CAS control signals to memory and for expanding the number of address bits employed to address memory chips having a greater number of addresses by at least one address bit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to memory access control logic circuits.More particularly, the present invention relates to a novel multi-modecontroller for accessing a plurality for different types of commerciallyavailable dynamic random access memory chips (DRAM) which form a mainstorage unit (MSU) of a computer.

2. Description of the Prior Art

Main storage units (MSUs) are typically used with main frame computers.More recently, powerful micro processor chips of the type made by Inteland Motorola have been incorporated into small powerful computingsystems which incorporate therein large amounts of dynamic random accessmemory (DRAM) storage. The trend toward faster computing speeds and theuse of reduced instruction set chips (RISC) in workstations of the typeused for graphics, simulation and various computer-aided design (CAD),computer-aided engineering (CAE) and computer aided manufacturing (CAM),have imposed a need for faster active memory chips and larger sizes ofthe memory storage.

One way to increase the speed of DRAM memory chips is to reduce the sizeof the discreet devices on the chips and/or to place more memory cellson the same chip or real estate. Another way of accomplishing fastermemory access is to employ a chip that is inherently faster by virtue ofits design and logic families such as ECL technology versus TTLtechnology and also the type of memory such as page mode verses staticcolumn mode designs.

When designing a computer for use with memory boards or MSUs, it wouldbe desirable to work with DRAM memory chips of the latest and fastestcommercially available design that is also cost efficient, thus, themainframe computer should be capable of accepting different size memorychips as well as different types of memory chips.

SUMMARY OF THE INVENTION

It is a principal object of the present invention to provide a DRAMcontroller capable of addressing various size and types of commerciallyavailable DRAM chips.

It is another principle object of the present invention to provide amultiple mode DRAM controller for accessing different size, type andspeed DRAMs.

It is a principle object of the present invention to provide amultiple-mode controller for addressing single or multiple words in MSUscomprising different operational type DRAMS.

It is another object of the present invention to provide a single DRAMcontroller for use with three of more different type of DRAM chips.

It is another object of the present invention to provide a novel DRAMcontroller which may be set in a different operational mode at thefactory or in the field.

It is the general object of the present invention to provide a novelDRAM controller which enables a computer to accept larger and fasterDRAM chips as they become commercially available and economicallyfeasible.

According to these and other objects of the present invention there isprovided a novel multi-mode DRAM contoller adapted to access DRAM chips,of different size and at least three different operational typesincluding Nibble mode, Page mode and Static mode types by convertingcommand register information from one mode to information usable by adifferent mode DRAM, and for expanding the limited addresses for a smallDRAM chip to a larger number addresses for a larger DRAM chip.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the present invention multi-mode readdata controller and associated MSU having a system bus architectureenvironment;

FIG. 2 is a detailed block diagram of the address generation controllogic for accessing the DRAM memory shown in FIG. 1;

FIG. 3 is a more detailed block diagram of the up/down controlleremployed in the control logic of FIG. 2; and

FIG. 4 is a schematic wave form diagram showing the common control waveforms used to access any dynamic type of RAM memory and the specificsubsequent control wave forms which are employed to access threedifferent types of DRAM memory.

DETAILED DESCRIPTION OF THE PEREFERRED EMBODIMENT

Refer now to FIG. 1 showing a block diagram of the present inventionwhich is incorporated into a prior art system bus architure environment.FIG. 1 basically comprises one of up to four MSUs 10 which are employedin a mainframe computer environment. MSU 10 is shown comprising a threeMeg by forty-three bit RAM memory which is the largest memory to beaccessed with the specific invention to be described hereinafter. Anormal RAM memory for the present invention computer is the same sizebut employs four times as many smaller RAM chips. The prior art RAM chipsize was 256K bits and the most modern commercially feasible RAM chip isa one Meg RAM chip which requires nine address bits instead of eightaddress bits as formerly used for a 256K normal MSU memory.

The system bus architure of the present invention employs a system bus11 which connects to the main CPU and the input output devices throughcontrollers not shown. An instruction type address on system bus 11 froma CPU, etc. is presented to the interface bus transceiver 12. Thetransceiver 12 is connected via a 47 line bus 13 to a controller 14which comprises an instruction/address controller portion 15 and asequence generator controller portion 16.

In the prior art mainframe computer a controller like controller 14would generate an address signal which could be coupled directly to theRAM memory array 17 comprising 256K chips. However, when the larger andmore dense one Meg RAM memory chips are employed the address formerllyused to address the 256K memory chips must be modified to include a newaddress comprising an additional bit in order to automatically make thisaddress expansion conversion. A novel new address generation controllogic circuit 18 is provided between the controller 14 and the RAMmemory array 17. As will be explained in greater detail hereinafter, theold address will be expanded and the row address signals (RAS) andcolumn address signals (CAS) which contain the synchronizing informationwill be delayed and modified so as to synchronize the new address withthe expanded memory 17. In this regard, the information on line 19 willbe shown to contain address bit information and the information on line21 will contain the RAS/CAS information. The information on line 22 willcontain information for controlling the novel up/down control of the newaddress generation control logic 18. The output line 23 from thesequence generator 16 is shown coupled to the data path logic 24 havingan output bus 25 which is connected as an input to the memory array 17.During a write operation, the information on bus 25 is written directlyinto the memory array 17 without modification. However, during a readoperation the output from the memory array 17 on read bus 26 is passedthrough a selector 27 under control of control line 28 from the sequencegenerator 16. The output from the selector 27 on bus 29 is errorcorrected and parity checked in logic 24 and produces the correctedinformation on line 25 and on branch bus 31. The corrected informationon branch bus 31 is always passed through the data path logic 24 and theinterface transceiver 12 for presentation on system bus 11. Thecorrected information on bus 25 is written over the previous informationin memory array 17, however if not corrected, it need not be writtenover the information in the memory array 17.

Bi-directional control lines 32 and 33 are shown connected between theinterface bus tranceiver 12 and the controller 14. A control line 34 inshown connected between the two control arrays 15 and 16. Wheninformation is to be written into the memory array 17, it is presentedon system bus 11 at transciever 12 and passed by write data bus 35,selector 27, bus 29 and data path logic 24 to bus 25. The write datapresented to data path logic 24 is parity checked and the generatedparity check bits on bus 25 are written into memory array 17 along withthe data.

Refer now to FIG. 2 showning a more detailed block diagram of theaddress generation control logic 18 shown in FIG. 1. The column addresssignals (CAS) are shown applied to line 21 as an input to CAS flip-flop36 to produce a Q output on line 37 which is applied to an AND gate 38along with a CAS input signal to produce a delayed new CAS signal onoutput line 20. The new CAS output signal on line 20 is shown in FIG. 1applied to the RAM memory array 17 as are the other output signals whichwill be explained hereinafter. Three different mutually exclusive rowaddress signals (RAS) signals will be applied to line 21 to access oneof three memory banks in the memory array 17. The RAS signals on line 21and the phase one clock signal on line 41 are applied to the RAS delaylatch 39 to produce the desired new or modified delayed RAS signals onoutput line 20.

The memory address signals on line 19 (also shown in FIG. 1) are appliedto the memory address latch 42 along with an enable signal on line 43 toproduce the desired delayed memory address bits 0 through 7 on outputline 20. In similar manner, the eighth memory address bit on line 19 isshown being applied to the row and column inputs of a 4 to 1 Mux 44along with two additional inputs, to be explained hereinafter. Mux 44produces the 9th adddress bit (New ADR 9) on line 20 as shown. The inputto Mux 44 on line 45 from two bit counter 46 is the column 9 address bitas will be explained in greater detail hereinafter. The input on line 47to Mux 44 is the row 9 input from encoder 48. Line 47 also generates thecolumn 8 input to Mux 49. Encoder 48 also produces the row 8 outputsignal on line 51 which is applied to two of the row/column inputs ofMux 49. A fourth input to Mux 49 is provided by 2 bit counter 46 as acolumn 8 input on line 52.

Mode selection switch 53 is shown having two possible selections. Thenot nibble (NOT N) and nibble terminals of switch 53 are applied as modeselection inputs to Mux 49 and Mux 44 via line 54. A further row/columntime selection input to Mux 49 and Mux 44 is shown at input line 55. Mux49 and Mux 44 produce the new address bit 8 and new address bit 9respectively as will now be explained. The information on input line 22to up/down control 56 along with a RAS quarter input signal on line 21is shown producing an output on line 57. The output signal on line 57determines the direction of the count in 2 bit counter 46 and usuallycounts up from 00 to 11 before resetting but is capable of counting downdepending on the type of operation presented on information line 22.

It will be understood that the RAS quarter information on line 21 waspreviously supplied by the controller 14 directly to the RAM memoryarray 17 to select one of the four 256K chips within a one Meg bank thatis now employed to provide information which may be encoded into addressinformation for one Meg chips. The information on line 21 which isapplied to encoder 48 produces the encoded row 8 information on line 51and the row 9 column 8 information on line 47 which is applied to theMux 49 and the Mux 44 as shown. With the information outputted from 2bit counter 46 and encoder 48, a new address bit 8 and a new address bit9 is produces on output line 20 as shown from Mux 49 and Mux 44respectively. It will now be understood that all of the informationshown in FIG. 2 output lines 20 is shown as input information on FIG. 1to the 3 Meg RAM array 17 shown in FIG. 1.

The old refresh signal line 58 is shown applied as an input to newrefresh logic 59 along with a clock signal on line 61. Ordinarily thesignal on line 58 would be used to initiate a refresh signal in a oneMeg bank of four 256K chips. The refresh requirements for a 3 Meg bankof 1 Meg chips requires that the refresh signal on line 58 be modifiedto produce the equivalent of two refresh signals for each refresh signalin the smaller memory array. The new logic refresh signal on line 62comprises a CAS before RAS sequence of signals which informs the largermemory chips to perform a refresh operation. It will be understood thatthe refresh operation for the larger RAM memory array is designed toaccept such logic signals and the timing is provided by the controller14 which produces the clock signal on line 61.

Refer now to FIG. 3 showing a more detailed block diagram of the up/downcontrol 56 employed in the control logic 18. The output line 57 from theup/down control 56 shown in FIG. 2 is shown in FIG. 3 as providing an upcount on line 57U and a down count on line 57D and having the followinginputs. Phase 2 and phase 4 clock inputs are shown on line 63 as aninputs to up/down control 56 along with the RAS quarter (1-4) inputsignal on line 21. The bypass line 22, shown as an output from sequencegenerator 16 in FIG. 1, is shown as four input lines to the up/downcontrol 56 for enabling the up/down control 56 to make a logicdetermination as to the type of instruction that is being performed. Theinputs labled enable error code generation, port selection 0 and 2, andwrite address 1 are employed to make this determination.

Refer now to FIG. 4 showing four sets of schematic wave form diagrams.The first set of four wave form diagrams are labled common timingsequence for first access and comprise a new address 0 to 9 signal whichappears on line 20 in FIG. 1 and also appears on lines 20 as the outputsof latch 42, Mux 49 and Mux 44 of FIG. 2.

The new RAS signal is shown generated on a line in bus 20 (also shown inFIG. 1 and in FIG. 2 as the output of latch 39). This signal is clockedor timed by a phase 1 input signal. The new CAS signal is timed by flipflop 36 on the trailing edge of a phase 3 signal to produce a low activesignal on line 20. In similar manner the read data signal may beavailable on line 25 (or subsequently on line 26) but must occur beforethe mid point of the phase 2 cycle on line 26 as shown.

The second set of wave forms shown in FIG. 4 are for the nibble modesubsequent accesses occuring at the input to the RAM array 17. Twocycles after the occurance of the row and column address in the firstsequence, the new address 0 to 9 reaches a "don't care" state at line 20shown as line 64. The new RAS signal at line 65 stays low active for theduration of the read or write operation. The new CAS signal 66 is showngoing from its low active state to high inactive during the beginning ofphase 4 and only lasting for the duration of a phase 4 cycle beforegoing low active. The read data on line 67 remains valid during the sametime period that new CAS is low active on line 66. In order to achivethe nibble mode the switch 53 in FIG. 2 must be toggled to the nibbleterminal so that mode line 54 is in the nibble mode.

The third sequence of wave forms are shown as the page mode subsequentaccesses wherein the address 0 to 9 is shown as wave form 68. The columnenvelop signal 68 is indicative of the column address and maintains anenabled state over a period of four phases or one cycle. The RAS signal65 is shown as previously still maintaining its low active state duringthe duration of the sequence. As previously described, the CAS signal islow active and goes high inactive during phase 4 and drops back to anactive state at the end of phase 4 and is shown being approximatelycentered during the time sequence of the enabling envelope of thecolumns at wave form 68. The read data signal on line 67 is enabledduring the CAS low active signal time 66 and is disabled during the CAShigh or inactive signal time.

The page mode sequence and the fourth set of static column subsequentaccess waveforms are activated by having the mode switch 53 in the notnibble mode (N). The four wave forms 68, 65, 66 and 67 for the staticcolumn sequence are identical to the page mode sequence and are numberedthe same.

It will be understood that the wave forms shown in FIG. 4 are thosegenerated on bus 20 and are applied to the RAM memory 17 to perform theread or write operations described hereinbefore. The switch 53 whichselects the mode may be a physical switch or a hard wired switchincorporated in the address generation control logic 18 and must beproperly set to conform to the type of DRAM to be used in the MSU.

Having explained a perferred embodiment of the present invention it willbe understood that the MSU 10 shown in FIG. 1 is a modified MSU whichincludes new address generating control logic 18 which enables differenttypes and sizes of RAM memory array 17 to be incorporated into the sameor different computers. Stated differently, the previous control logiccan be employed with the new address generation control logic 18 withoutmodification when using a small prior art 256K memory chip array. Thecontrol logic 18 is also employed when using the modern, more dense andfaster 1 Mega bit memory array chips. Further, the same inventionconcept may be employed for expanding memories for other types ofcomputers by using the new address generation control logic foraddressing more dense and larger memory arrays using the same initialcontrol signals employed for prior art memories.

What is claimed is:
 1. A multi-mode DRAM controller for accessingdifferent size and operational mode types of RAM memory chipscomprising:a RAM memory to be accessed having a greater number of memoryaddresses than is provided in a normal memory controller; access controlmeans for generating normal column and row address signals and forgenerating normal instructions and normal sequences of operation toaccess addresses in a normal size RAM memory; new address logic meanscoupled between said RAM memory and said access control means; said newaddress logic means comprising latch means for generating delayed normalcolumn and row address signals, said new address logic means furthercomprising column and row encoding means for generating additionalcolumn and row address signals indicative of a greater number of memoryaddresses than contained in a normal size RAM memory, said new addresslogic means further comprising means for synchronizing said additionalcolumn and row address signals with said delayed normal column and rowaddress signals to provide new column and row address signals togetherhaving a greater capacity to define said greater number of memoryaddresses in said RAM memory, said means for synchronizing saidadditional column and row address signals comprises multiplexor meanscoupled to said column and row encoding means for generating said newcolumn and row address signals; and mode switch selection means in saidnew address logic means for selecting different operational mode typesof larger RAM memory chips to be addressed.
 2. A multi-mode DRAMcontroller as set forth in claim 1 wherein said access control meanscomprises means for generating a normal column address signal CAS andnormal address information for addressing a normal size memory, and saidnew address logic means further includes flip flop means coupled to saidCAS address signal to provide delayed CAS output signals for addressinglarger size memory chips.
 3. A multi-mode DRAM controller as set forthin claim 1 wherein said access control means comprises means forgenerating a normal row address signal RAS and normal addressinformation for addressing a normal size memory, and said new addresslogic means further includes latch means coupled to said RAS outputsignal for providing delayed RAS output signals for addressing largersize memory chips.
 4. A multi-mode DRAM controller as said forth inclaim 1 wherein said access control means comprises means for generatinga column and row memory address for the most significant address bits ofsaid larger RAM memory chips, and said new address logic means furtherincludes latch means coupled to said most significant address bits forproviding said delayed normal column and row memory address signals. 5.A multi-mode DRAM controller as set forth in claim 1 wherein said accesscontrol means comprises means for generating a least significant addressbit signal, and said multiplexor means further includes a pair ofmultiplexors coupled to said access control means for providing a pairof new address least significant bits as output address signals.
 6. Amulti-mode DRAM controller as set forth in claim 5 wherein said newaddress logic means further includes an up/down control having inputscoupled to said access control means and an output coupled to a two bitcounter, said counter having an output coupled to said pair ofmultiplexors to provide two new least significant address bits as anoutput.
 7. A multi-mode DRAM controller as set forth in claim 6 whereinsaid new address logic means further includes an encoder coupled to theinput of said pair of multiplexors for providing said two new leastsignificant bits as an output.